It is known that III-N based devices, such as GaN semiconductor devices, grown on a silicon substrate require gate dielectric material with sufficient dielectric constant and a proper band offset for good operating characteristics, e.g. low leakage currents and good gate control. In the prior art some attempts at using high-k polycrystalline materials have been unsuccessful. For example, polycrystalline Hf2O3 has been proposed for a gate dielectric. However, the material was found to be unsuitable because of leakage current paths via nanocrystallite grain boundaries and because of crystal defects induced high interface state density which deteriorate electrical properties of the material.
In the semiconductor industry, it is also known that growing a III-N material, such as GaN, on a silicon substrate is difficult due in large part to the large crystal lattice mismatch (−16.9%) and the thermal mismatch (53%) between silicon and GaN. Thus, some type of buffer layer or layers is generally formed on the silicon substrate and the III-N material is grown on the buffer layer. Generally, the prior art buffer layers are either, complicated and expensive to form or do no adequately reduce the strain in the GaN due to crystal lattice mismatch.
Further, once a semiconductor device is formed in the III-N material with improved gate dielectric material a gate electrode is formed. In the prior art the gate electrode was formed by some metallization process in which Ti/Al/Au based material was deposited. This deposition is expensive and requires at least one additional step in the fabrication.
It would be highly advantageous, therefore, to remedy the foregoing and other deficiencies inherent in the prior art.
Accordingly, it is an object of the present invention to provide a new and improved gate electrode for III-N devices on silicon substrates.
It is another object of the present invention to provide new and improved methods for the formation of a gate electrode in III-N devices on silicon substrates.
It is another object of the present invention to provide new and improved methods for the growth of III-N devices on a silicon substrate that includes substantially reducing strain in the active III-N material as well as the formation of a gate dielectric and a gate electrode in one continuous (in-situ) operation.
It is another object of the present invention to provide a new and improved gate electrode for III-N devices.